Proceedings Paper, 2024

Modeling and Simulation for DRAM and Flash Memory Technology Exploration and Development

2024 IEEE INTERNATIONAL MEMORY WORKSHOP, IMW, ISSN 2330-7978, ISBN 979-8-3503-0652-1, 10.1109/IMW59701.2024.10536984

Contributors

Lin, Xi-Wei (Corresponding author) [1] Amoroso, S. [2] Lee, Ko-Hsin [3] Ke, Meng Hsuan [3] Gunst, Tue [4] Tikhomirov, Pavel [5] Asenov, Plamen [2] IEEE

Affiliations

  1. [1] Synopsys Inc, Sunnyvale, CA 94085 USA
    2. [NORA names: United States; America, North; OECD];
  2. [2] Synopsys Northen Europe Ltd, Glasgow, Lanark, Scotland
    3. [NORA names: United Kingdom; Europe, Non-EU; OECD];
  3. [3] Synopsys Taiwan, Hsinchu, Taiwan
    4. [NORA names: Taiwan; Asia, East];
  4. [4] Synopsys Denmark, Copenhagen, Denmark
    5. [NORA names: Other Companies; Private Research; Denmark; Europe, EU; Nordic; OECD];
  5. [5] Synopsys Switzerland LLC, Zurich, Switzerland
    6. [NORA names: Switzerland; Europe, Non-EU; OECD]

Abstract

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Keywords

3D DRAM, 3D NAND, 4F2, DRAM, RTN, TCAD, ab initio, floating body effect, program noise, row hammer, simulations, variability, vertical channel transistor, wafer warpage

Data Provider: Clarivate

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